A 65 nm CMOS technology for mobile and digital signal processing applications

A. Chatterjee, J. Yoon, S. Zhao, S. Tang, K. Sadra, S. Crank, H. Mogul, R. Aggarwal, B. Chatterjee, S. Lytle, C. T. Lin, K. D. Lee, J. Kim, Q. Z. Hong, T. Kim, L. Olsen, M. Quevedo-Lopez, K. Kirmse, G. Zhang, C. MeekD. Aldrich, H. Mair, M. Mehrotra, L. Adam, D. Mosher, J. Y. Yang, D. Crenshaw, B. Williams, J. Jacobs, M. Jain, J. Rosal, T. Houston, J. Wu, N. S. Nagaraj, D. Scott, S. Ashburn, A. Tsao

Research output: Contribution to conferencePaper

26 Scopus citations

Abstract

This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/ mm 2 and a SRAM memory density of 1.4 Mb/mm 2 using a sub-0.49 um 2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described. ©2004 IEEE.
Original languageAmerican English
Pages665-668
Number of pages4
StatePublished - 1 Dec 2004
Externally publishedYes
EventTechnical Digest - International Electron Devices Meeting, IEDM -
Duration: 1 Dec 2004 → …

Conference

ConferenceTechnical Digest - International Electron Devices Meeting, IEDM
Period1/12/04 → …

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