Abstract
This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/ mm 2 and a SRAM memory density of 1.4 Mb/mm 2 using a sub-0.49 um 2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described. ©2004 IEEE.
Original language | American English |
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Pages | 665-668 |
Number of pages | 4 |
State | Published - 1 Dec 2004 |
Externally published | Yes |
Event | Technical Digest - International Electron Devices Meeting, IEDM - Duration: 1 Dec 2004 → … |
Conference
Conference | Technical Digest - International Electron Devices Meeting, IEDM |
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Period | 1/12/04 → … |