A 65 nm CMOS technology for mobile and digital signal processing applications

A. Chatterjee; J. Yoon; S. Zhao; S. Tang; K. Sadra; S. Crank; H. Mogul; R. Aggarwal; B. Chatterjee; S. Lytle; C. T. Lin; K. D. Lee; J. Kim; Q. Z. Hong; T. Kim; L. Olsen; M. Quevedo-Lopez; K. Kirmse; G. Zhang; C. Meek; D. Aldrich; H. Mair; M. Mehrotra; L. Adam; D. Mosher; J. Y. Yang; D. Crenshaw; B. Williams; J. Jacobs; M. Jain; J. Rosal; T. Houston; J. Wu; N. S. Nagaraj; D. Scott; S. Ashburn; A. Tsao

A 65 nm CMOS technology for mobile and digital signal processing applications

A. Chatterjee, J. Yoon, S. Zhao, S. Tang, K. Sadra, S. Crank, H. Mogul, R. Aggarwal, B. Chatterjee, S. Lytle, C. T. Lin, K. D. Lee, J. Kim, Q. Z. Hong, T. Kim, L. Olsen, M. Quevedo-Lopez, K. Kirmse, G. Zhang, C. MeekD. Aldrich, H. Mair, M. Mehrotra, L. Adam, D. Mosher, J. Y. Yang, D. Crenshaw, B. Williams, J. Jacobs, M. Jain, J. Rosal, T. Houston, J. Wu, N. S. Nagaraj, D. Scott, S. Ashburn, A. Tsao

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26 Scopus citations

Abstract

This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/ mm 2 and a SRAM memory density of 1.4 Mb/mm 2 using a sub-0.49 um 2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described. ©2004 IEEE.

Original language	American English
Pages	665-668
Number of pages	4
State	Published - 1 Dec 2004
Externally published	Yes
Event	Technical Digest - International Electron Devices Meeting, IEDM - Duration: 1 Dec 2004 → …

Conference

Conference	Technical Digest - International Electron Devices Meeting, IEDM
Period	1/12/04 → …

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Chatterjee, A., Yoon, J., Zhao, S., Tang, S., Sadra, K., Crank, S., Mogul, H., Aggarwal, R., Chatterjee, B., Lytle, S., Lin, C. T., Lee, K. D., Kim, J., Hong, Q. Z., Kim, T., Olsen, L., Quevedo-Lopez, M., Kirmse, K., Zhang, G., ... Tsao, A. (2004). A 65 nm CMOS technology for mobile and digital signal processing applications. 665-668. Paper presented at Technical Digest - International Electron Devices Meeting, IEDM. https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=21644450840&origin=inward

@conference{74e08ff98c7d4e18bc87bd4474c499b9,

title = "A 65 nm CMOS technology for mobile and digital signal processing applications",

abstract = "This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/ mm 2 and a SRAM memory density of 1.4 Mb/mm 2 using a sub-0.49 um 2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described. {\textcopyright}2004 IEEE.",

author = "A. Chatterjee and J. Yoon and S. Zhao and S. Tang and K. Sadra and S. Crank and H. Mogul and R. Aggarwal and B. Chatterjee and S. Lytle and Lin, {C. T.} and Lee, {K. D.} and J. Kim and Hong, {Q. Z.} and T. Kim and L. Olsen and M. Quevedo-Lopez and K. Kirmse and G. Zhang and C. Meek and D. Aldrich and H. Mair and M. Mehrotra and L. Adam and D. Mosher and Yang, {J. Y.} and D. Crenshaw and B. Williams and J. Jacobs and M. Jain and J. Rosal and T. Houston and J. Wu and Nagaraj, {N. S.} and D. Scott and S. Ashburn and A. Tsao",

year = "2004",

month = dec,

day = "1",

language = "American English",

pages = "665--668",

note = "Technical Digest - International Electron Devices Meeting, IEDM ; Conference date: 01-12-2004",

}

Chatterjee, A, Yoon, J, Zhao, S, Tang, S, Sadra, K, Crank, S, Mogul, H, Aggarwal, R, Chatterjee, B, Lytle, S, Lin, CT, Lee, KD, Kim, J, Hong, QZ, Kim, T, Olsen, L, Quevedo-Lopez, M, Kirmse, K, Zhang, G, Meek, C, Aldrich, D, Mair, H, Mehrotra, M, Adam, L, Mosher, D, Yang, JY, Crenshaw, D, Williams, B, Jacobs, J, Jain, M, Rosal, J, Houston, T, Wu, J, Nagaraj, NS, Scott, D, Ashburn, S & Tsao, A 2004, 'A 65 nm CMOS technology for mobile and digital signal processing applications', Paper presented at Technical Digest - International Electron Devices Meeting, IEDM, 1/12/04 pp. 665-668. <https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=21644450840&origin=inward>

TY - CONF

T1 - A 65 nm CMOS technology for mobile and digital signal processing applications

AU - Chatterjee, A.

AU - Yoon, J.

AU - Zhao, S.

AU - Tang, S.

AU - Sadra, K.

AU - Crank, S.

AU - Mogul, H.

AU - Aggarwal, R.

AU - Chatterjee, B.

AU - Lytle, S.

AU - Lin, C. T.

AU - Lee, K. D.

AU - Kim, J.

AU - Hong, Q. Z.

AU - Kim, T.

AU - Olsen, L.

AU - Quevedo-Lopez, M.

AU - Kirmse, K.

AU - Zhang, G.

AU - Meek, C.

AU - Aldrich, D.

AU - Mair, H.

AU - Mehrotra, M.

AU - Adam, L.

AU - Mosher, D.

AU - Yang, J. Y.

AU - Crenshaw, D.

AU - Williams, B.

AU - Jacobs, J.

AU - Jain, M.

AU - Rosal, J.

AU - Houston, T.

AU - Wu, J.

AU - Nagaraj, N. S.

AU - Scott, D.

AU - Ashburn, S.

AU - Tsao, A.

PY - 2004/12/1

Y1 - 2004/12/1

N2 - This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/ mm 2 and a SRAM memory density of 1.4 Mb/mm 2 using a sub-0.49 um 2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described. ©2004 IEEE.

AB - This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/ mm 2 and a SRAM memory density of 1.4 Mb/mm 2 using a sub-0.49 um 2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described. ©2004 IEEE.

M3 - Paper

SP - 665

EP - 668

T2 - Technical Digest - International Electron Devices Meeting, IEDM

Y2 - 1 December 2004

ER -

A 65 nm CMOS technology for mobile and digital signal processing applications

Abstract

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