A compact drain current model for thin-film transistor under bias stress condition

Rodolfo Garcia*, Israel Mejia, Julio Tinoco, Jesus Ezequiel Molinar-Solis, Alejandra Morales, Miguel Aleman, Sergio Sandoval, Manuel A. Quevedo-Lopez

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


Several basic thin-film transistor (TFT) models have been developed to describe the electrical characteristics of the device, most of them only considering the fundamental instability effects during static mode operation. However, representing the dynamic behavior is also a major concern for circuit design due to the electrical stress changes over time. Under this scenario, empirical models have been previously demonstrated to reproduce the current instability effects under specific conditions, but they do not consider in detail the phenomena taking place when the TFT is under dynamic electrical stress. In this paper, a new semianalytical model is presented to describe the dynamical behavior of the TFT under stress. This model considers the impact of the negative charge trapped at interfacial states as well as the mobility degradation. To validate the model, we compare the results with experimental measurements from our group, (using CdS TFT), and other semiconductor TFTs (a-Si:H, SnO, IZO, and IGZO) reported by other authors.

Original languageEnglish
Pages (from-to)1803-1809
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number5
StatePublished - May 2018
Externally publishedYes

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  • Bias stress
  • channel conductivity
  • current instability
  • modeling
  • thin-film transistor (TFT)
  • trapped charge


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