TY - JOUR
T1 - A compact drain current model for thin-film transistor under bias stress condition
AU - Garcia, Rodolfo
AU - Mejia, Israel
AU - Tinoco, Julio
AU - Molinar-Solis, Jesus Ezequiel
AU - Morales, Alejandra
AU - Aleman, Miguel
AU - Sandoval, Sergio
AU - Quevedo-Lopez, Manuel A.
N1 - Publisher Copyright:
© 1963-2012 IEEE.
PY - 2018/5
Y1 - 2018/5
N2 - Several basic thin-film transistor (TFT) models have been developed to describe the electrical characteristics of the device, most of them only considering the fundamental instability effects during static mode operation. However, representing the dynamic behavior is also a major concern for circuit design due to the electrical stress changes over time. Under this scenario, empirical models have been previously demonstrated to reproduce the current instability effects under specific conditions, but they do not consider in detail the phenomena taking place when the TFT is under dynamic electrical stress. In this paper, a new semianalytical model is presented to describe the dynamical behavior of the TFT under stress. This model considers the impact of the negative charge trapped at interfacial states as well as the mobility degradation. To validate the model, we compare the results with experimental measurements from our group, (using CdS TFT), and other semiconductor TFTs (a-Si:H, SnO, IZO, and IGZO) reported by other authors.
AB - Several basic thin-film transistor (TFT) models have been developed to describe the electrical characteristics of the device, most of them only considering the fundamental instability effects during static mode operation. However, representing the dynamic behavior is also a major concern for circuit design due to the electrical stress changes over time. Under this scenario, empirical models have been previously demonstrated to reproduce the current instability effects under specific conditions, but they do not consider in detail the phenomena taking place when the TFT is under dynamic electrical stress. In this paper, a new semianalytical model is presented to describe the dynamical behavior of the TFT under stress. This model considers the impact of the negative charge trapped at interfacial states as well as the mobility degradation. To validate the model, we compare the results with experimental measurements from our group, (using CdS TFT), and other semiconductor TFTs (a-Si:H, SnO, IZO, and IGZO) reported by other authors.
KW - Bias stress
KW - channel conductivity
KW - current instability
KW - modeling
KW - thin-film transistor (TFT)
KW - trapped charge
UR - http://www.scopus.com/inward/record.url?scp=85045205650&partnerID=8YFLogxK
U2 - 10.1109/TED.2018.2818694
DO - 10.1109/TED.2018.2818694
M3 - Artículo
SN - 0018-9383
VL - 65
SP - 1803
EP - 1809
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 5
ER -