A polylogarithmic model for thin-film transistors used in a CMOS inverter amplifier

This article presents a generalization of a transregional polylogarithmic model, previously proposed for continuously describing the transfer characteristics of polycrystalline and amorphous Thin Film Transistors (TFTs) at all levels of inversion. The present generalization entails including the necessary drain voltage dependencies to be able to describe also the output characteristics. The model is tested by using it in the design and analysis of a CMOS inverter amplifier consisting of poly-Si n- and p-channel TFTs fabricated at low temperature and pressure. The transistors are biased below threshold so that the CMOS amplifier circuit operates in weak conduction, having in mind energy saving considerations. The validity of the proposed model has been ascertained by comparing model simulations to actual measured data from individual poly-Si TFTs and from the CMOS amplifier circuit. The simulations of the CMOS inverter amplifier are compared to the results obtained using look-up table-type simulations.