Band edge n-MOSFETs with high-k/metal gate stacks scaled to EOT=0.9nm with excellent carrier mobility and high temperature stability

P. D. Kirsch, M. A. Quevedo-Lopez, S. A. Krishnan, C. Krug, H. AlShareef, C. S. Park, R. Harris, N. Moumen, A. Neugroschel, G. Bersuker, B. H. Lee, J. G. Wang, G. Pant, B. E. Gnade, M. J. Kim, R. M. Wallace, J. S. Jur, D. J. Lichtenwalner, A. I. Kingon, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

18 Scopus citations

Abstract

We demonstrate, for the first time, a HfLaSiON/metal gate stack that concurrently achieves the following: low threshold voltage (V T=0.33V), low equivalent oxide thickness (EOT=0.91nm) (T inv=1.3nm) and 83% SiO2 mobility. Key enablers of this result are 1) La doped HfSiON for n-FET VT tuning 2) HfO 2:SiO2 alloy ratio with 10% SiO2 suppressing crystallization up to 1070°C, 3) interlayer SiO2 (IL) to reduced bias temperature instability (BTI) and 4) plasma nitridation (N*)/post nitridation anneal (PNA) sequence for EOT scaling. This work advances high-k/band edge metal gate (MG) efforts by showing scalability of HfLaSiON to EOT=0.91nm without mobility or BTI trade-off, while matching the VT of a SiO2/n-PolySi control.

Original languageEnglish
Title of host publication2006 International Electron Devices Meeting Technical Digest, IEDM
DOIs
StatePublished - 2006
Event2006 International Electron Devices Meeting, IEDM - San Francisco, CA, United States
Duration: 10 Dec 200613 Dec 2006

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2006 International Electron Devices Meeting, IEDM
Country/TerritoryUnited States
CitySan Francisco, CA
Period10/12/0613/12/06

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