TY - JOUR
T1 - CdS Thin Film Transistor for Inverter and Operational Amplifier Circuit Applications
AU - Wondmagegn, W.
AU - Mejia, I.
AU - Salas-Villasenor, A.
AU - Stiegler, H. J.
AU - Quevedo-Lopez, M. A.
AU - Pieper, R. J.
AU - Gnade, B. E.
PY - 2016/5/1
Y1 - 2016/5/1
N2 - © 2016 Elsevier B.V. All rights reserved. Organic and inorganic thin film transistors (TFTs) are fabricated, simulated, and tested for circuit applications. The devices are based on polycrystalline cadmium sulfide (CdS) and pentacene thin films. Both devices are simulated and analyzed using two-dimensional finite element simulation methodology. For CdS, grain boundary and uniform trap distribution approaches are implemented. It is assumed that traps due to grain boundaries are uniformly distributed throughout the film. For pentacene a Poole-Frenkel mobility model is employed. After matching device simulation with experimental data, the SPICE model parameters are extracted for circuit simulation. The devices are tested for both analog and digital circuits. operational amplifier (OPAMP) and inverter circuits are tested. Two OPAMP topologies are compared and the results are discussed. One of the topologies is based on all n-type transistors using CdS TFT and the other topology is the two-stage Miller compensated CMOS design based on CdS and pentacene TFTs. The operational amplifiers have an open-loop voltage gain of 25.9 dB and 29.7 dB respectively. The performance of the CMOS design is found to be limited by performance of pentacene transistor.
AB - © 2016 Elsevier B.V. All rights reserved. Organic and inorganic thin film transistors (TFTs) are fabricated, simulated, and tested for circuit applications. The devices are based on polycrystalline cadmium sulfide (CdS) and pentacene thin films. Both devices are simulated and analyzed using two-dimensional finite element simulation methodology. For CdS, grain boundary and uniform trap distribution approaches are implemented. It is assumed that traps due to grain boundaries are uniformly distributed throughout the film. For pentacene a Poole-Frenkel mobility model is employed. After matching device simulation with experimental data, the SPICE model parameters are extracted for circuit simulation. The devices are tested for both analog and digital circuits. operational amplifier (OPAMP) and inverter circuits are tested. Two OPAMP topologies are compared and the results are discussed. One of the topologies is based on all n-type transistors using CdS TFT and the other topology is the two-stage Miller compensated CMOS design based on CdS and pentacene TFTs. The operational amplifiers have an open-loop voltage gain of 25.9 dB and 29.7 dB respectively. The performance of the CMOS design is found to be limited by performance of pentacene transistor.
U2 - 10.1016/j.mee.2016.02.042
DO - 10.1016/j.mee.2016.02.042
M3 - Article
SN - 0167-9317
SP - 64
EP - 70
JO - Microelectronic Engineering
JF - Microelectronic Engineering
ER -