Gate first high-k/metal gate stacks with zero SiO<inf>x</inf> interface achieving EOT=0.59nm for 16nm application

J. Huang, D. Heh, P. Sivasubramani, P. D. Kirsch, G. Bersuker, D. C. Gilmer, M. A. Quevedo-Lopez, M. M. Hussain, P. Majhi, P. Lysaght, H. Park, N. Goel, C. Young, C. S. Park, C. Park, M. Cruz, V. Diaz, P. Y. Hung, J. Price, H. H. TsengR. Jammy

Research output: Contribution to conferencePaper

41 Scopus citations
Original languageAmerican English
Pages34-35
Number of pages2
StatePublished - 16 Nov 2009
EventDigest of Technical Papers - Symposium on VLSI Technology -
Duration: 16 Nov 2009 → …

Conference

ConferenceDigest of Technical Papers - Symposium on VLSI Technology
Period16/11/09 → …

Fingerprint Dive into the research topics of 'Gate first high-k/metal gate stacks with zero SiO<inf>x</inf> interface achieving EOT=0.59nm for 16nm application'. Together they form a unique fingerprint.

  • Cite this

    Huang, J., Heh, D., Sivasubramani, P., Kirsch, P. D., Bersuker, G., Gilmer, D. C., Quevedo-Lopez, M. A., Hussain, M. M., Majhi, P., Lysaght, P., Park, H., Goel, N., Young, C., Park, C. S., Park, C., Cruz, M., Diaz, V., Hung, P. Y., Price, J., ... Jammy, R. (2009). Gate first high-k/metal gate stacks with zero SiO<inf>x</inf> interface achieving EOT=0.59nm for 16nm application. 34-35. Paper presented at Digest of Technical Papers - Symposium on VLSI Technology, .