Identification of logic paths influenced by severe coupling capacitances

I. D. Meza-Ibarra; V. Champac; R. Gomez-Fuentes; J. R. Noriega; A. Vera-Marquina

doi:10.1109/LATW.2019.8704636

Identification of logic paths influenced by severe coupling capacitances

I. D. Meza-Ibarra, V. Champac, R. Gomez-Fuentes, J. R. Noriega, A. Vera-Marquina

Departamento de Investigación en Física

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Modern integrated circuits present complex interconnect structures, in which the signal coupling play an important role in the overall circuit behavior. In this paper, a method to identify those logic paths more significantly influenced by signals at coupled lines is presented. This method can be used to validate circuit behavior and can also be applied in testing techniques oriented to detect interconnect defects (e.g. opens and short defects). A modified Dijkstra's algorithm is used to find those paths between a primary input and a primary output with higher coupling capacitances. This methodology is applied to ISCAS'85 benchmark circuits.

Original language	English
Title of host publication	LATS 2019 - 20th IEEE Latin American Test Symposium
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728117560
DOIs	https://doi.org/10.1109/LATW.2019.8704636
State	Published - 1 May 2019
Event	20th IEEE Latin American Test Symposium, LATS 2019 - Santiago, Chile Duration: 11 Mar 2019 → 13 Mar 2019

Publication series

Name	LATS 2019 - 20th IEEE Latin American Test Symposium

Conference

Conference	20th IEEE Latin American Test Symposium, LATS 2019
Country/Territory	Chile
City	Santiago
Period	11/03/19 → 13/03/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

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10.1109/LATW.2019.8704636

Cite this

Meza-Ibarra, I. D., Champac, V., Gomez-Fuentes, R., Noriega, J. R., & Vera-Marquina, A. (2019). Identification of logic paths influenced by severe coupling capacitances. In LATS 2019 - 20th IEEE Latin American Test Symposium Article 8704636 (LATS 2019 - 20th IEEE Latin American Test Symposium). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LATW.2019.8704636

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title = "Identification of logic paths influenced by severe coupling capacitances",

abstract = "Modern integrated circuits present complex interconnect structures, in which the signal coupling play an important role in the overall circuit behavior. In this paper, a method to identify those logic paths more significantly influenced by signals at coupled lines is presented. This method can be used to validate circuit behavior and can also be applied in testing techniques oriented to detect interconnect defects (e.g. opens and short defects). A modified Dijkstra's algorithm is used to find those paths between a primary input and a primary output with higher coupling capacitances. This methodology is applied to ISCAS'85 benchmark circuits.",

author = "Meza-Ibarra, {I. D.} and V. Champac and R. Gomez-Fuentes and Noriega, {J. R.} and A. Vera-Marquina",

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year = "2019",

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doi = "10.1109/LATW.2019.8704636",

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Meza-Ibarra, ID, Champac, V, Gomez-Fuentes, R , Noriega, JR & Vera-Marquina, A 2019, Identification of logic paths influenced by severe coupling capacitances. in LATS 2019 - 20th IEEE Latin American Test Symposium., 8704636, LATS 2019 - 20th IEEE Latin American Test Symposium, Institute of Electrical and Electronics Engineers Inc., 20th IEEE Latin American Test Symposium, LATS 2019, Santiago, Chile, 11/03/19. https://doi.org/10.1109/LATW.2019.8704636

Identification of logic paths influenced by severe coupling capacitances. / Meza-Ibarra, I. D.; Champac, V.; Gomez-Fuentes, R. et al.
LATS 2019 - 20th IEEE Latin American Test Symposium. Institute of Electrical and Electronics Engineers Inc., 2019. 8704636 (LATS 2019 - 20th IEEE Latin American Test Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Modern integrated circuits present complex interconnect structures, in which the signal coupling play an important role in the overall circuit behavior. In this paper, a method to identify those logic paths more significantly influenced by signals at coupled lines is presented. This method can be used to validate circuit behavior and can also be applied in testing techniques oriented to detect interconnect defects (e.g. opens and short defects). A modified Dijkstra's algorithm is used to find those paths between a primary input and a primary output with higher coupling capacitances. This methodology is applied to ISCAS'85 benchmark circuits.

AB - Modern integrated circuits present complex interconnect structures, in which the signal coupling play an important role in the overall circuit behavior. In this paper, a method to identify those logic paths more significantly influenced by signals at coupled lines is presented. This method can be used to validate circuit behavior and can also be applied in testing techniques oriented to detect interconnect defects (e.g. opens and short defects). A modified Dijkstra's algorithm is used to find those paths between a primary input and a primary output with higher coupling capacitances. This methodology is applied to ISCAS'85 benchmark circuits.

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 20th IEEE Latin American Test Symposium, LATS 2019

Y2 - 11 March 2019 through 13 March 2019

ER -

Identification of logic paths influenced by severe coupling capacitances

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