Quantum Confinement and Interface States in ZnO Nanocrystalline Thin-Film Transistors

Richard A. Chapman, Rodolfo A. Rodriguez-Davila, William G. Vandenberghe, Christopher L. Hinkle, Israel Mejia, Amitava Chatterjee, Manuel A. Quevedo-Lopez

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


© 1963-2012 IEEE. The experimental current-voltage ( {I}-{D} - {V}-{G} ) and capacitance-voltage ( {C} - {V}-{G} ) characteristics of the bottom-gate/top-contact ZnO thin-film transistors (TFTs) are analyzed accounting for quantum confinement and interface state effects. All the measurements are performed on the same TFTs composed of a 45-nm-thick nanocrystalline ZnO channel, indium tin oxide gate electrode, and a 21-nm-thick Al2O3 gate insulator. Interface state density (Dit) derived from the combined high-low frequency capacitance method reveals a large Dit near the conduction band edge. The TFT characteristics are simulated using a Schrodinger-Poisson model and compared to a semiclassical model. The Schrodinger-Poisson model calculates a lower C in accumulation by correctly accounting for the peak carrier concentration being several nanometers away from the ZnO/Al2O3 interface. The fit error in {C} - {V}-{G} in strong accumulation is only 1.2% compared to 4% in the semiclassical simulations. All simulations are performed using 21 nm of Al2O3. An effective mobility ( \mu -{\mathrm{ eff}} ) that increases linearly with gate voltage is derived from the ratio of the experimental {I}-{D} and the simulated mobile charge per unit area of the channel. Ignoring quantum confinement overestimates the channel charge and hence underestimates \mu -{\mathrm{ eff}} by 40%. An additional Dit profile, at the top interface of the ZnO, is proposed in our analysis to explain the {I}-{D} - {V}-{G} characteristics in the subthreshold region.
Original languageAmerican English
Pages (from-to)1787-1795
Number of pages9
JournalIEEE Transactions on Electron Devices
StatePublished - 1 May 2018
Externally publishedYes


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