A 65 nm CMOS technology for mobile and digital signal processing applications

A. Chatterjee; J. Yoon; S. Zhao; S. Tang; K. Sadra; S. Crank; H. Mogul; R. Aggarwal; B. Chatterjee; S. Lytle; C. T. Lin; K. D. Lee; J. Kim; Q. Z. Hong; T. Kim; L. Olsen; M. Quevedo-Lopez; K. Kirmse; G. Zhang; C. Meek; D. Aldrich; H. Mair; M. Mehrotra; L. Adam; D. Mosher; J. Y. Yang; D. Crenshaw; B. Williams; J. Jacobs; M. Jain; J. Rosal; T. Houston; J. Wu; N. S. Nagaraj; D. Scott; S. Ashburn; A. Tsao

A 65 nm CMOS technology for mobile and digital signal processing applications

A. Chatterjee^*, J. Yoon, S. Zhao, S. Tang, K. Sadra, S. Crank, H. Mogul, R. Aggarwal, B. Chatterjee, S. Lytle, C. T. Lin, K. D. Lee, J. Kim, Q. Z. Hong, T. Kim, L. Olsen, M. Quevedo-Lopez, K. Kirmse, G. Zhang, C. MeekD. Aldrich, H. Mair, M. Mehrotra, L. Adam, D. Mosher, J. Y. Yang, D. Crenshaw, B. Williams, J. Jacobs, M. Jain, J. Rosal, T. Houston, J. Wu, N. S. Nagaraj, D. Scott, S. Ashburn, A. Tsao

^*Autor correspondiente de este trabajo

Departamento de Investigación en Polímeros y Materiales

Producción científica: Contribución a una revista › Artículo de la conferencia › revisión exhaustiva

27 Citas (Scopus)

Resumen

This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/ mm ² and a SRAM memory density of 1.4 Mb/mm ² using a sub-0.49 um ² bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.

Idioma original	Inglés
Páginas (desde-hasta)	665-668
Número de páginas	4
Publicación	Technical Digest - International Electron Devices Meeting, IEDM
Estado	Publicada - 2004
Evento	IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, Estados Unidos Duración: 13 dic. 2004 → 15 dic. 2004

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Chatterjee, A., Yoon, J., Zhao, S., Tang, S., Sadra, K., Crank, S., Mogul, H., Aggarwal, R., Chatterjee, B., Lytle, S., Lin, C. T., Lee, K. D., Kim, J., Hong, Q. Z., Kim, T., Olsen, L., Quevedo-Lopez, M., Kirmse, K., Zhang, G., ... Tsao, A. (2004). A 65 nm CMOS technology for mobile and digital signal processing applications. Technical Digest - International Electron Devices Meeting, IEDM, 665-668.

@article{d4a10b0645d642d996a6a2e69526c2eb,

title = "A 65 nm CMOS technology for mobile and digital signal processing applications",

abstract = "This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/ mm 2 and a SRAM memory density of 1.4 Mb/mm 2 using a sub-0.49 um 2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.",

author = "A. Chatterjee and J. Yoon and S. Zhao and S. Tang and K. Sadra and S. Crank and H. Mogul and R. Aggarwal and B. Chatterjee and S. Lytle and Lin, {C. T.} and Lee, {K. D.} and J. Kim and Hong, {Q. Z.} and T. Kim and L. Olsen and M. Quevedo-Lopez and K. Kirmse and G. Zhang and C. Meek and D. Aldrich and H. Mair and M. Mehrotra and L. Adam and D. Mosher and Yang, {J. Y.} and D. Crenshaw and B. Williams and J. Jacobs and M. Jain and J. Rosal and T. Houston and J. Wu and Nagaraj, {N. S.} and D. Scott and S. Ashburn and A. Tsao",

note = "Funding Information: The authors are grateful for contributions from Drs. Bob Eklund, Urning Ko, Venu Menon, and Dennis Buss, the SiTD/KFAB process teams, the SiTD RET team, and the SPICE modeling lab.; IEEE International Electron Devices Meeting, 2004 IEDM ; Conference date: 13-12-2004 Through 15-12-2004",

year = "2004",

language = "Ingl{\'e}s",

pages = "665--668",

journal = "Technical Digest - International Electron Devices Meeting, IEDM",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

Chatterjee, A, Yoon, J, Zhao, S, Tang, S, Sadra, K, Crank, S, Mogul, H, Aggarwal, R, Chatterjee, B, Lytle, S, Lin, CT, Lee, KD, Kim, J, Hong, QZ, Kim, T, Olsen, L, Quevedo-Lopez, M, Kirmse, K, Zhang, G, Meek, C, Aldrich, D, Mair, H, Mehrotra, M, Adam, L, Mosher, D, Yang, JY, Crenshaw, D, Williams, B, Jacobs, J, Jain, M, Rosal, J, Houston, T, Wu, J, Nagaraj, NS, Scott, D, Ashburn, S & Tsao, A 2004, 'A 65 nm CMOS technology for mobile and digital signal processing applications', Technical Digest - International Electron Devices Meeting, IEDM, pp. 665-668.

TY - JOUR

T1 - A 65 nm CMOS technology for mobile and digital signal processing applications

AU - Chatterjee, A.

AU - Yoon, J.

AU - Zhao, S.

AU - Tang, S.

AU - Sadra, K.

AU - Crank, S.

AU - Mogul, H.

AU - Aggarwal, R.

AU - Chatterjee, B.

AU - Lytle, S.

AU - Lin, C. T.

AU - Lee, K. D.

AU - Kim, J.

AU - Hong, Q. Z.

AU - Kim, T.

AU - Olsen, L.

AU - Quevedo-Lopez, M.

AU - Kirmse, K.

AU - Zhang, G.

AU - Meek, C.

AU - Aldrich, D.

AU - Mair, H.

AU - Mehrotra, M.

AU - Adam, L.

AU - Mosher, D.

AU - Yang, J. Y.

AU - Crenshaw, D.

AU - Williams, B.

AU - Jacobs, J.

AU - Jain, M.

AU - Rosal, J.

AU - Houston, T.

AU - Wu, J.

AU - Nagaraj, N. S.

AU - Scott, D.

AU - Ashburn, S.

AU - Tsao, A.

N1 - Funding Information: The authors are grateful for contributions from Drs. Bob Eklund, Urning Ko, Venu Menon, and Dennis Buss, the SiTD/KFAB process teams, the SiTD RET team, and the SPICE modeling lab.

PY - 2004

Y1 - 2004

N2 - This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/ mm 2 and a SRAM memory density of 1.4 Mb/mm 2 using a sub-0.49 um 2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.

AB - This paper presents a 65 nm CMOS technology that achieves a logic density of 900 k-gates/ mm 2 and a SRAM memory density of 1.4 Mb/mm 2 using a sub-0.49 um 2 bitcell. Key features of a low cost technology option for mobile products (MP) and a high performance technology option (HP) for DSP based applications are described.

UR - http://www.scopus.com/inward/record.url?scp=21644450840&partnerID=8YFLogxK

M3 - Artículo de la conferencia

AN - SCOPUS:21644450840

SN - 0163-1918

SP - 665

EP - 668

JO - Technical Digest - International Electron Devices Meeting, IEDM

JF - Technical Digest - International Electron Devices Meeting, IEDM

T2 - IEEE International Electron Devices Meeting, 2004 IEDM

Y2 - 13 December 2004 through 15 December 2004

ER -

A 65 nm CMOS technology for mobile and digital signal processing applications

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