Identification of Logic Paths Influenced by Severe Coupling Capacitances

I. D. Meza-Ibarra, V. Champac, R. Gomez-Fuentes*, J. R. Noriega, A. Vera-Marquina

*Autor correspondiente de este trabajo

Resultado de la investigación: Contribución a una revistaArtículorevisión exhaustiva


Signals in modern integrated circuits travel through complex interconnect structures, which present several layers and important coupling capacitance effects. Even more, the impact of signal coupling on the overall circuit behavior has grown with technology scaling as the interconnect have become taller. In this paper, a methodology to identify those logic paths more significantly influenced by the coupling capacitances is presented. The proposed methodology is based on a modified Dijkstra’s algorithm, which finds those paths between a primary input and a primary output more severely influenced by the coupling capacitances. This methodology can be used to validate circuit behavior and it can also be applied in testing techniques oriented to detect interconnect defects (e.g., opens and short defects). The proposed methodology is applied to ISCAS’85 benchmark circuits to show its feasibility.

Idioma originalInglés
Páginas (desde-hasta)731-741
Número de páginas11
PublicaciónJournal of Electronic Testing: Theory and Applications (JETTA)
EstadoPublicada - dic 2020

Nota bibliográfica

Publisher Copyright:
© 2020, Springer Science+Business Media, LLC, part of Springer Nature.


Profundice en los temas de investigación de 'Identification of Logic Paths Influenced by Severe Coupling Capacitances'. En conjunto forman una huella única.

Citar esto