Semi empirical cadmium sulfide transistor model combining grain defects and semiconductor thickness variation

Naga Surya Pasupuleti, Ron Pieper, Wudyalew Wondmagegn, Andrew L. Coogan, Israel Mejia, Ana Salas-Villasenor, Manuel Quevedo-Lopez

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

Resumen

Proposed and tested is a methodology for modeling polycrystalline thin film transistors which exhibit shifts in threshold voltage due to both grain boundaries and semiconductor thickness. The process involves a model, which uses in part standard-analytic terms. It also includes terms for grain defects and for thickness added in using numerical simulation testing. From this testing, the threshold voltage for the CdS transistor exhibited an optimum thickness for enhancement mode operation. The semi empirical model was then brought into alignment with experimental results for a CdS transistor by adjusting the interface charge. Predictions from the semi empirical model produced transistor output characteristic and transfer curves showed to be in good agreement with experimental data.

Idioma originalInglés
Título de la publicación alojada45th Southeastern Symposium on System Theory, SSST 2013
Páginas6-11
Número de páginas6
DOI
EstadoPublicada - 2013
Publicado de forma externa
Evento45th Southeastern Symposium on System Theory, SSST 2013 - Waco, TX, Estados Unidos
Duración: 11 mar. 201311 mar. 2013

Serie de la publicación

NombreProceedings of the Annual Southeastern Symposium on System Theory

Conferencia

Conferencia45th Southeastern Symposium on System Theory, SSST 2013
País/TerritorioEstados Unidos
CiudadWaco, TX
Período11/03/1311/03/13

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