Systematic gate stack optimization to maximize mobility with HfSiON EOT scaling

M. A. Quevedo-Lopez, P. D. Kirsch, S. Krishnan, H. N. Alshareef, J. Barnett, H. R. Harris, A. Neugroschel, F. S. Aguirre-Tostado, B. E. Gnade, M. J. Kim, R. M. Wallace, B. H. Lee

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3 Citas (Scopus)

Resumen

A systematic study to optimize gate stack constituents (interface, high- κ, metal gate) to maximize carrier mobility with aggressively scaled equivalent oxide thickness (EOT) is presented. We identify ultra-thin thermal oxide, atomic layer deposited HfSiON and optimized plasma nitridation performed in sequence as the optimized run path for sub-nm EOT scaling with high carrier mobility. A metal gate deposition process that minimizes the incorporation of impurities in HfSiON is also vital to maintaining good mobility at low EOTs.

Idioma originalInglés
Título de la publicación alojadaESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference
EditorialIEEE Computer Society
Páginas113-116
Número de páginas4
ISBN (versión impresa)1424403014, 9781424403011
DOI
EstadoPublicada - 2006
Publicado de forma externa
EventoESSDERC 2006 - 36th European Solid-State Device Research Conference - Montreux, Suiza
Duración: 19 sep. 200621 sep. 2006

Serie de la publicación

NombreESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference
Volumen2006-January

Conferencia

ConferenciaESSDERC 2006 - 36th European Solid-State Device Research Conference
País/TerritorioSuiza
CiudadMontreux
Período19/09/0621/09/06

Nota bibliográfica

Publisher Copyright:
©2006 IEEE.

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