Technology and reliability challenges of SUB-nm EOT high-κ/ metal gate electrode transistors

There are numerous challenges in scaling the Hf-based hieh-k dielectric gate stack to sub-mn equivalent oxide thickness (EOT): bottom interface thickness and k-value, high-k initiation and growth, and elimination of interfacial reactions such as occurs between the poly-silicon gate electrode and high-k dielectric. In addition, the high-k/poly-Si gate stack faces challenges in obtaining the desired flat-band voltage and threshold voltage and transistor integration challenges in using metal gate electrodes. In terms of electrical performance, high-k transistors face the challenge of resolving mobility and drive current degradation. Finally, high levels of interface and bulk charge at the bottom interfacial oxide layer and high-k dielectric layer, respectively, dominate the long-term stability and reliability behavior of transistors built using these gate stacks. In this paper, several approaches to successful resolution of these challenges are presented demonstrating finished transistor (1000C/10s anneal) EOTs as low as 0.51 nm for HfD₂ gate dielectrics, and peak mobilities of 214 Cm²ATs and high field mobilities of 189 Cm²/Vs at EOT of 0.96 nm.