Resumen
Back-gate ZnO TFTs - with and without top-side passivation - were fabricated and electrically characterized. Passivation layers consisting of HfO2, Al2O3, and Parylene were introduced to study their impact on the TFT performance. Annealing was done to improve the electrical characteristics of passivated devices by neutralizing the initial charge introduced as a result of the low-temperature passivation. Low-temperature annealing combined with an Al2O3passivation layer demonstrates an I-V response comparable to ZnO TFTs without any passivation layer, indicating the viability of Al2O3as a good candidate for passivating ZnO TFTs.
Idioma original | Inglés |
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Título de la publicación alojada | 2019 IEEE 32nd International Conference on Microelectronic Test Structures, ICMTS 2019 |
Editorial | Institute of Electrical and Electronics Engineers Inc. |
Páginas | 190-193 |
Número de páginas | 4 |
ISBN (versión digital) | 9781728114668 |
DOI | |
Estado | Publicada - mar. 2019 |
Publicado de forma externa | Sí |
Evento | 32nd IEEE International Conference on Microelectronic Test Structures, ICMTS 2019 - Kitakyushu City, Fukuoka Prefecture, Japón Duración: 18 mar. 2019 → 21 mar. 2019 |
Serie de la publicación
Nombre | IEEE International Conference on Microelectronic Test Structures |
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Volumen | 2019-March |
Conferencia
Conferencia | 32nd IEEE International Conference on Microelectronic Test Structures, ICMTS 2019 |
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País/Territorio | Japón |
Ciudad | Kitakyushu City, Fukuoka Prefecture |
Período | 18/03/19 → 21/03/19 |
Nota bibliográfica
Publisher Copyright:© 2019 IEEE.