Understanding the effects of low-temperature passivation and annealing on ZnO TFTs test structures

Rodolfo A. Rodriguez-Davila, Pavel Bolshakov, Chadwin D. Young, Manuel Quevedo-Lopez

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

1 Cita (Scopus)

Resumen

Back-gate ZnO TFTs - with and without top-side passivation - were fabricated and electrically characterized. Passivation layers consisting of HfO2, Al2O3, and Parylene were introduced to study their impact on the TFT performance. Annealing was done to improve the electrical characteristics of passivated devices by neutralizing the initial charge introduced as a result of the low-temperature passivation. Low-temperature annealing combined with an Al2O3passivation layer demonstrates an I-V response comparable to ZnO TFTs without any passivation layer, indicating the viability of Al2O3as a good candidate for passivating ZnO TFTs.

Idioma originalInglés
Título de la publicación alojada2019 IEEE 32nd International Conference on Microelectronic Test Structures, ICMTS 2019
EditorialInstitute of Electrical and Electronics Engineers Inc.
Páginas190-193
Número de páginas4
ISBN (versión digital)9781728114668
DOI
EstadoPublicada - mar. 2019
Publicado de forma externa
Evento32nd IEEE International Conference on Microelectronic Test Structures, ICMTS 2019 - Kitakyushu City, Fukuoka Prefecture, Japón
Duración: 18 mar. 201921 mar. 2019

Serie de la publicación

NombreIEEE International Conference on Microelectronic Test Structures
Volumen2019-March

Conferencia

Conferencia32nd IEEE International Conference on Microelectronic Test Structures, ICMTS 2019
País/TerritorioJapón
CiudadKitakyushu City, Fukuoka Prefecture
Período18/03/1921/03/19

Nota bibliográfica

Publisher Copyright:
© 2019 IEEE.

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